@article{oai:fukuyama-u.repo.nii.ac.jp:00008079,
 author = {三宅, 雅保},
 journal = {福山大学工学部紀要},
 month = {Dec},
 note = {P(論文), High-frequency capacitance-voltage (C-V) characteristics of a buried-channel MOS capacitor have been measured and analyzed. The C-V characteristics, including transient behavior, of a buried-channel MOS capacitor that has a counter-doped p layer at the surface of n substrate are very similar to those of a surface-channel MOS capacitor of n substrate if the counter-doped layer is shallow enough to be fully inverted at large positive bias. As gate voltage is decreased, equilibrium capacitance for inversion (accumulation for the counter-doped layer) reaches a minimum value and then slightly increases to saturate, which is peculiar to a buried-channel MOS capacitor. This behavior arises from the fact that hole distribution is changed by the high-frequency gate-voltage change for the measurement signal although total amount of holes is not changed.},
 pages = {1--6},
 title = {埋め込みチャネルMOSキャパシタのC-V特性},
 volume = {25},
 year = {2001}
}